Self-biased oscillator

ABSTRACT

Described herein is a phase-locked loop including a phase detector, a charge pump, a filter, and a self-biased voltage-controlled oscillator having an oscillating frequency controlled by a control signal. The self-biased voltage-controlled oscillator includes a first differentiator and a second differentiator. The second differentiator has an input node coupled to the output node of the first differentiator, and an output node coupled to the input node of the first differentiator. In one embodiment, each of the first and the second differentiators has adjustable resistance and/or capacitance, and the oscillating frequency of the voltage-controlled oscillator is independent of power supply provided to the first and the second differentiators.

CLAIM OF PRIORITY

This application claims the benefit of priority of International PatentApplication No. PCT/US2012/029647 filed Mar. 19, 2012, titled“SELF-BIASED OSCILLATOR,” and co-pending U.S. patent application Ser.No. 13/995,487 filed Jun. 18, 2013, titled “SELF-BIASED OSCILLATOR,”which are incorporated by reference in its entirety.

BACKGROUND

Traditional voltage controlled oscillator (VCO) exhibits an oscillatingfrequency that depends on the power supply level provided to the VCO. Asthe power supply level increases, the oscillating frequency increasesbecause the delay elements forming the VCO become faster. Likewise, whenthe power supply level decreases, the oscillating frequency decreases.Such traditional VCO exhibit power supply noise sensitivity that mayresult in noise/jitter in the output of the VCO.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the disclosure will be understood more fully from thedetailed description given below and from the accompanying drawings ofvarious embodiments of the disclosure, which, however, should not betaken to limit the disclosure to the specific embodiments, but are forexplanation and understanding only.

FIG. 1 is a high level circuit of a self-biased oscillator, according toone embodiment of the disclosure.

FIG. 2 is a self-biased oscillator, according to one embodiment of thedisclosure.

FIG. 3 is a voltage controlled resistive device of the self-biasedoscillator, according to one embodiment of the disclosure.

FIG. 4 is a voltage controlled resistive device of the self-biasedoscillator, according to another embodiment of the disclosure.

FIG. 5 is a digitally controlled resistive device of the self-biasedoscillator, according to one embodiment of the disclosure.

FIG. 6 is a phase locked loop (PLL) with the self-biased oscillator,according to one embodiment of the disclosure.

FIG. 7 is a digital phase locked loop (DPLL) with the self-biasedoscillator, according to one embodiment of the disclosure.

FIG. 8 is a system-level diagram of a smart device comprising aprocessor with the self-biased oscillator, according to one embodimentof the disclosure.

DETAILED DESCRIPTION

Traditional voltage controlled oscillators (VCOs) such as an inverterbased ring oscillator, a pseudo-differential inverter ring, aself-biased current-mode-logic (CML) ring, etc, exhibit high sensitivityto power supply noise. High sensitivity to power supply noise translatesto jitter and noise in the oscillating signal generated by the VCO. Tocompensate for the high sensitivity of power supply noise, traditionaloscillators are made larger in size (W/L) resulting in higher powerdissipation and area.

Ring oscillator topologies often used in phase locked loops (PLLs) dueto their large frequency tuning range, however, have poor performance(as defined by power supply rejection ratio) when it comes to noiserejection. Self-biased differential ring oscillators have better noiserejection than inverter based traditional ring oscillators yet at aconsiderable power/area cost. Poor performance of these ring oscillatorsis because the oscillation frequency (f_(o)) of these oscillators is adirect function of their power supply (Vcc). The oscillation frequency(f_(o)) of such traditional oscillators can be expressed as:

$f_{0} \cong \frac{I}{N \cdot C \cdot {Vcc}}$

where, ‘N’ is the number of delay stages of the oscillator, and where‘I’ is the current through output capacitance ‘C’ of the oscillator. Theabove equation shows that f_(o) is inversely proportional to the powersupply Vcc. Any noise on the power supply Vcc may translate to jitterand noise on the oscillating signal with frequency f_(o).

The self-biased oscillator discussed herein provides better power supplyrejection than traditional VCOs because the oscillating frequency of theoutput of the self-biased oscillator is not a function (or not a strongfunction) of power supply or gain of the delay element or amplifier ofthe self-biased oscillator. In one embodiment, the self-biasedoscillator is self-biased by its feedback resistor. The self-biasedoscillator discussed herein consumes far less power than apseudo-differential inverter ring oscillator or a self-biased CML ringoscillator, and consumes much less area than traditional oscillators.The self-biased oscillator can be used in any oscillator usage modelincluding analog phase locked loops and digital phase locked loops. Theself-biased oscillator discussed herein comprises an inverter, variableresistance and/or capacitance, which makes the design simple and highlyscalable over process technologies. Other technical effects arecontemplated by the embodiments discussed herein.

The term “scaling” herein refers generally to transferring the circuitdesign and layout from one process technology to another processtechnology.

In the following description, numerous details are discussed to providea more thorough explanation of embodiments of the present disclosure. Itwill be apparent, however, to one skilled in the art, that embodimentsof the present disclosure may be practiced without these specificdetails. In other instances, well-known structures and devices are shownin block diagram form, rather than in detail, in order to avoidobscuring embodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals arerepresented with lines. Some lines may be thicker, to indicate moreconstituent signal paths, and/or have arrows at one or more ends, toindicate primary information flow direction. Such indications are notintended to be limiting. Rather, the lines are used in connection withone or more exemplary embodiments to facilitate easier understanding ofa circuit or a logical unit. Any represented signal, as dictated bydesign needs or preferences, may actually comprise one or more signalsthat may travel in either direction and may be implemented with anysuitable type of signal scheme.

Throughout the specification, and in the claims, the term “connected”means a direct electrical connection between the things that areconnected, without any intermediary devices. The term “coupled” meanseither a direct electrical connection between the things that areconnected, or an indirect connection through one or more passive oractive intermediary devices. The term “circuit” means one or morepassive and/or active components that are arranged to cooperate with oneanother to provide a desired function. The term “signal” means at leastone current signal, voltage signal or data/clock signal. The meaning of“a”, “an”, and “the” include plural references. The meaning of “in”includes “in” and “on”.

As used herein, unless otherwise specified the use of the ordinaladjectives “first,” “second,” and “third,” etc., to describe a commonobject, merely indicate that different instances of like objects arebeing referred to, and are not intended to imply that the objects sodescribed must be in a given sequence, either temporally, spatially, inranking or in any other manner. The term “substantially” herein refersto being within 10% of the target.

For purposes of the embodiments described herein, the transistors aremetal oxide semiconductor (MOS) transistors, which include drain,source, gate, and bulk terminals. Source and drain terminals may beidentical terminals and are interchangeably used herein. Those skilledin the art will appreciate that other transistors, for example, Bi-polarjunction transistors—BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be usedwithout departing from the scope of the disclosure. The terms “MN”herein indicates an n-type transistor (e.g., NMOS, NPN BJT, etc) and theterm “MP” indicates a p-type transistor (e.g., PMOS, PNP BJT, etc).

FIG. 1 is a high level circuit of a self-biased oscillator 100,according to one embodiment of the disclosure. In one embodiment, theself-biased oscillator 100 comprises a first differentiator 101 coupledto a second differentiator 102 forming an oscillator. The firstdifferentiator 101 and the second differentiator 102 are circuitsproviding outputs which are proportional to the time derivative of theinput.

In this embodiment, the output node Out of the first differentiator 101is coupled to the input of the second differentiator 102, and the outputnode of the second differentiator 102 is coupled to the input node ofthe first differentiator. In one embodiment, both the firstdifferentiator 101 and second differentiator 102 are powered by thepower supply. The noise of the power supply has little or no effect onthe oscillating frequency of the oscillator 100.

In one embodiment, the gain or transfer function of the firstdifferentiator is the same as the gain or transfer function of thesecond differentiator. In another embodiment, the gain or transferfunction of the first differentiator is different from the gain ortransfer function of the second differentiator.

The circuit 100 discussed herein results in a signal on the output nodeOut to have an oscillating frequency. In one embodiment, a controlsignal Vctrl is input to both the first and second differentiators 101and 102, respectively, to adjust the oscillation frequency of the signalon the output node Out. In one embodiment, the control signal Vctrl isan analog signal to control a resistance and/or capacitance of atransistor. In another embodiment, the control signal Vctrl is a digitalbus to turn on/off a number of transistors in the first and seconddifferentiators 101 and 102, respectively, to change the resistanceand/or capacitance of the first and second differentiators 101 and 102,respectively.

FIG. 2 is a self-biased oscillator 200, according to one embodiment ofthe disclosure. In one embodiment, each of the first and seconddifferentiators 101 and 102, respectively, comprise: amplifiers 201 and211, resistive devices 202 and 212, and capacitive devices 203 and 213,coupled together as shown. In one embodiment, the resistive devices 202and 212 having resistance R_(f) are coupled between the output node ofthe amplifiers 201 and 211 and input nodes of the amplifiers 201 and211. In one embodiment, the resistance R_(f) of the resistive devices202 and 212 is adjustable by means of the control signal Vctrl.

For example, a transistor is used for providing the effective resistanceR_(f), where the control signal couples to the gate of the transistorand controls the resistance of the transistor. In another embodiment, atransistor is coupled to a passive resistor or active resistor (e.g.,always on transistor) for providing the resistance R_(f), where thecontrol signal couples to the gate of the transistor and controls theresistance of the transistor and thus the combined resistance R_(f)(combined resistance of the passive or active resistor and thetransistor). In another example, the control signal is a digital bus toturn on/off any number of transistors coupled together in parallel toone another to provide resistance R_(f). In one embodiment, only thetransistor(s) provides the effective resistance R_(f) i.e., there is nopassive resistor coupled to the transistor(s).

In one embodiment, the amplifiers 201 and 211 have a gain of −A (whereA=Vo/Vin). In one embodiment, the amplifiers 201 and 211 are invertershaving a p-type device coupled in series to an n-type device. In anotherembodiment, the amplifiers 201 and 211 are operational amplifiers(OPAMPs). In other embodiments, other forms of amplifiers may be used.

In one embodiment, the capacitive devices 203 and 213, having respectivefirst and second terminals, with their respective first terminalscoupled to the inputs 204 and 214 of the amplifiers 201 and 211. Thesecond terminals of the capacitive devices 203 and 213 form the inputsof the respective first and second differentiators 101 and 102. In thisembodiment, the second terminal of the capacitive device 213 (of thesecond differentiator 102) is coupled the output node Out of the firstdifferentiator 101. In this embodiment, the second terminal of thecapacitive device 203 is coupled to the output terminal In (also inputterminal of the first differentiator 101) of the second differentiator102.

In the embodiments discussed herein, the capacitive devices 203 and 213have a capacitance of C_(f). In one embodiment, the capacitive devices203 and 213 are passive devices. In other embodiments, the capacitivedevices 203 and 213 are formed from active devices such as transistorsoperating in capacitive modes. In other embodiments, the capacitivedevices 203 and 213 are implemented as varactors of any known design. Inone embodiment, the capacitive devices 203 and 213 are implemented byinterleaving layers of metal layers, also called metal capacitors. Inother embodiments, the capacitive devices 203 and 213 are implemented byinterleaving layers of metal layers and active transistors operable incapacitive mode. In one embodiment, the capacitive devices 203 and 213have variable capacitance controlled by the control signal Vctrl oranother control signal (not shown), different from the control voltagefor adjusting R_(f), for the capacitive devices 203 and 213 only.

In one embodiment, both resistive devices 202 and 212 and the capacitivedevices 203 and 213 have corresponding variable resistances andcapacitances controllable by control signals such as (and including)Vctrl. In another embodiment, only the resistive devices 202 and 212have variable resistances controllable by control signals such as (andincluding) Vctrl while the capacitance of the capacitive devices 203 and213 have fixed capacitances. In another embodiment, only the capacitivedevices 203 and 213 have variable capacitances controllable by controlsignals such as (and including) Vctrl while the resistances of theresistive devices (202 and 212) have fixed resistances.

The following small signal analysis of the first 101 and/or second 102differentiators comprising inverters as amplifiers 201 and 211illustrate that an oscillator formed from the first 101 and second 102differentiators coupled together as shown in FIG. 1 and FIG. 2 generatean output signal (on output node Out) with oscillating frequency whichis not a function of power supply or gain or the amplifiers 201 and 211.

The transfer function in s-domain of the first 101 and/or second 102differentiators can be expressed as:

${H(s)} = {\frac{V_{o}}{V_{i}} = \frac{- {sA}}{s + {{A/R_{f}}C_{f}}}}$

where ‘A’ is the gain of the inverter 201 or 211 expressed as the ratioof sum of trans-conductance of the p-type and n-type transistors of theinverter i.e., (g_(mn)+g_(mp))/(g_(op)+g_(on)), where V_(o) is theoutput voltage at the node Out and V_(i) is the input voltage at nodeIn, where R_(f) is the effective resistance of the feedback resistor202/212, and where C_(f) is the effective capacitance of capacitivedevice 203/213.

According to Bark-Hausen criteria for oscillation, the following issatisfied:

1+H(s)*H(s)=0

Solving the above equation leads to:

${s^{2} + {s\frac{2A}{\left( {A^{2} + 1} \right)R_{f}C_{f}}} + \frac{A^{2}}{\left( {A^{2} + 1} \right)\left( {R_{f}C_{f}} \right)^{2\;}}} = 0$

Assuming A²>>1, the solution to the above equation yields two right-halfplane pole pairs give as:

$s_{1,2} = {\frac{- 1}{R_{f}C_{f}}\left( {\frac{1}{A} \pm j} \right)}$

This shows that the oscillation will start and then the pole pair willmove to the line between right and left half planes so the oscillationis sustained. The frequency of oscillation of the self-biased oscillator100/200 is given as:

$f_{o} = \frac{1}{2{\pi \cdot R_{f}}C_{f}}$

The analysis herein illustrates that the frequency of oscillation of theself-biased oscillator 100/200 depends on the resistance R_(f) andcapacitance C_(f) of the corresponding feedback resistor 202/212 andcapacitive device 203/213 of the first 101 and/or second 102differentiators.

The analysis herein shows a fundamental difference between traditionalring oscillators which have oscillating frequencies that depend on powersupply voltage (Vcc), and therefore, the traditional ring-oscillatorsare more vulnerable to jitter from power supply noise.

FIG. 3 is a voltage controlled resistive device 300/202/212 of theself-biased oscillator 100/200, according to one embodiment of thedisclosure. The embodiment of FIG. 3 is described with reference toFIGS. 1-2. In this embodiment, the resistive device 300/202/212comprises a transistor with its gate terminal coupled to a controlsignal Vctrl. While the embodiments herein discuss an n-type transistorMN1, any transistor capable of providing adjustable resistance inresponse to changing voltage levels of the control signal Vctrl may beused.

For example, in one embodiment, the transistor is a p-type transistor.In another embodiment, the transistor is a combination of a p-type andn-type transistor (e.g., a transmission pass gate). While the embodimentherein shows a single transistor MN1, multiple transistors in series orparallel with one another may be used and controlled by the controlsignal Vctrl to provide an adjustable resistance.

In one embodiment, the transistor with adjustable resistance is coupledin series with another resistive device R₁ to provide the effectiveresistance R_(f). In one embodiment, the resistive device R₁ has a fixedresistance. In another embodiment, the resistive device R₁ isimplemented using a passive resistor e.g., a poly resistor, or discreteresistor. In other embodiments, other implementations of the resistivedevice R₁ may be used. For example, the resistive device R₁ is atransistor which is always on. In one embodiment, the resistive deviceR₁ is not used and the effective resistance R_(f) is provided by thetransistor MN1.

FIG. 4 is a voltage controlled resistive device 400/202/212 of theself-biased oscillator 100/200, according to another embodiment of thedisclosure. FIG. 4 is described with reference to FIGS. 1-2. In thisembodiment, a transistor to provide adjustable resistance is coupled inparallel to the resistive device R₁ to provide the effective resistanceR_(f). In one embodiment, the resistive device R₁ is not used and theeffective resistance R_(f) is provided by the parallel transistors.

While the embodiments herein describes an n-type transistor MN1, anytransistor capable of providing adjustable resistance in response tochanging voltage levels of the control signal Vctrl may be used.

For example, in one embodiment, the transistor is a p-type transistor.In another embodiment, the transistor is a combination of a p-type andn-type transistor (e.g., a transmission pass gate). While the embodimentherein shows a single transistor MN1, multiple transistors in series orparallel with one another may be used and controlled by the controlsignal Vctrl to provide an adjustable resistance.

In one embodiment, the resistive device R₁ has a fixed resistance. Inanother embodiment, the resistive device R₁ is implemented using apassive resistor e.g., a poly resistor, or discrete resistor. In otherembodiments, other implementations of the resistive device R₁ may beused. For example, the resistive device R₁ is a transistor which isalways on.

FIG. 5 is a digitally controlled resistive device 500/202/212 of theself-biased oscillator 100/200, according to one embodiment of thedisclosure. FIG. 5 is described with reference to FIGS. 1-2. In thisembodiment, a number of digitally controlled transistors are coupledtogether to provide adjustable resistance, and are coupled to theresistive device R₁ to provide the effective resistance R_(f). In oneembodiment, the resistive device R₁ is not used and the digitallycontrolled transistors provide the effective resistance R_(f).

In this embodiment, the control signal Vctrl is a digital busVctrl_digital[1:N] of ‘N’ bits, where ‘N’ is an integer greater or equalto 1. In one embodiment, each bit of the digital bus Vctrl_digital[1:N]is coupled to a gate terminal of a transistor which is operable to turnon or off according to the signal level of the coupled bit signal.

While the embodiment herein describes n-type transistors MN1 inparallel, any transistor capable of providing adjustable resistance inresponse to changing voltage levels of the control signal Vctrl may beused. For example, in one embodiment, the transistors are p-typetransistors. In another embodiment, the transistors are a combination ofa p-type and n-type transistors (e.g., a transmission pass gates). Whilethe embodiment herein shows transistors MN1-N in series with resistivedevice R₁, the transistors MN1-N may be in parallel to the resistivedevice R₁.

In one embodiment, the resistive device R₁ has a fixed resistance. Inanother embodiment, the resistive device R₁ is implemented using apassive resistor e.g., a poly resistor, or discrete resistor. In otherembodiments, other implementations of the resistive device R₁ may beused. For example, the resistive device R₁ is a transistor which isalways on.

FIG. 6 is a phase locked loop (PLL) 600 with the self-biased oscillator100/200, according to one embodiment of the disclosure. In oneembodiment, the PLL 600 comprises a phase detector 601, a charge pump602, a filter 603, an oscillator 100, and a divider 605. So as not toobscure the embodiments of the disclosure, a simplified PLL 600 isillustrated with details not shown.

In this embodiment, the self-biased oscillator 100/200 is used as avoltage controlled oscillator for the PLL 600, wherein the self-biasedoscillator 100/200 provides voltage adjustable output clock signal withlittle or no sensitivity to power supply noise on the power supply ofthe self-biased oscillator 100/200. In one embodiment, the phasedetector 601 compares a reference clock signal with a feedback clocksignal generated by dividing the output clock signal by a divider 605.In one embodiment, the output of the phase detector 601 is an up/dnsignal indicating whether the phase of the feedback clock signal isahead or behind the relative phase of the reference clock signal. Anyknown phase detector architecture may be used to implement the phasedetector 601.

In one embodiment, the output (up/dn signal) of the phase detector 601is received by the charge pump 602. In one embodiment, the charge pump602 generates currents or voltages (e.g., vcp) indicating whether thecontrol voltage Vctrl should be raised or lowered relative to itsprevious value. Any known charge pump may be used herein. In oneembodiment, the output of the charge pump vcp is filtered by an analogfilter e.g., an RC network to generate the control signal Vctrl tocontrol the resistance and/or capacitance of resistive devices 202/212and capacitive devices 203/213 of the self-biased oscillator 100/200. Inone embodiment, the resistive devices are the devices discussed withreference to FIGS. 3-4.

FIG. 7 is a digital phase locked loop (DPLL) 700 with the self-biasedoscillator 100/200, according to one embodiment of the disclosure. Inone embodiment, the DPLL 700 comprises a phase detector 601, acontroller or finite state machine (FSM) 701, a digital filter 702, adigital self-biased oscillator 100/200, and a divider 605. So as not toobscure the embodiments of the disclosure, a simplified DPLL 700 isillustrated with details not shown. In one embodiment, the digital phaselocked loop is an all digital phase locked loop (ADPLL).

In this embodiment, the self-biased oscillator 100/200 is used as adigitally controlled oscillator for the DPLL 700, wherein theself-biased oscillator 100/200 provides voltage adjustable output clocksignal with little or no sensitivity to power supply voltage of theself-biased oscillator 100/200. In one embodiment, the phase detector601 (as discussed with reference to FIG. 6) compares a reference clocksignal with a feedback clock signal generated by dividing the outputclock signal by a divider 605. In one embodiment, the output of thephase detector 601 is an up/dn signal indicating whether the phase ofthe feedback clock signal is ahead or behind the relative phase of thereference clock signal.

In one embodiment, the output up/dn signal of the phase detector 601 isreceived by the controller 701 which generates a digital code(s)indicating the step size and oscillating frequency setting of theself-biased DCO (digitally controlled oscillator) 100/200. In oneembodiment, the output code(s) of the controller 701 is received by thedigital filter 702 which filters noise in the code(s) and generate aVctrl_digital[1:N] signal as described with reference to FIG. 5. Theoutput of the DCO 100/200 is then divided by the divider 605 forcomparing the feedback signal with the reference clock signal.

The embodiments discussed herein provide several unexpected results,compared to traditional inverter ring oscillator, pseudo-differentialinverter ring oscillator, self-biased CML ring oscillator, withreference to oscillator performance parameters.

For example, the embodiments discussed herein provide lower power supplynoise rejection, lower peak-to-peak jitter, lower power dissipation,lower Kvcc GHz/V, lower Kvctrl GHz/V, and higher ratio of Kvctrl/Kvcc,where Kvcc is the oscillating frequency gain relative to change in powersupply voltage (Vcc), and where Kvctrl is the frequency gain of theoscillator relative to change in control voltage Vctrl.

Table 1 provides a comparison of performance parameters for fourdifferent oscillators including the self-biased oscillator 100/200. Thethree oscillators from the top are traditional oscillators. Theperformance results are based for a 1V power supply (Vcc) and anoscillator operable to provide an oscillating frequency range of 2-6GHz.

The parameter I(vcc) indicates the current consumed by the oscillator toprovide the same oscillating frequency at the same power supply level.The parameter “PSN” indicates peak-to-peak jitter in picoseconds for thesame power supply injected noise. The parameter Kvcc is the oscillatingfrequency gain relative to change in power supply voltage (Vcc). Theparameter Kvctrl is the frequency gain of the oscillator relative tochange in control voltage Vctrl. The parameter KVctrl/Kvcc is the powersupply sensitive with reference to control sensitivity.

TABLE 1 Comparison of performance parameters Kvctrl/ I(vcc) PSN KvctrlKvcc Kvcc Oscillator topology mA ps GHz/V GHz/V — TRADITIONAL: Inverterring 0.56 65.9 22.8 21.6 1.06 Pseudo-diff inv ring 1.44 48.3 16.9 16.61.02 Self-biased CML ring 13.00 38.5 16.2 6.4 2.53 Self-biasedoscillator 0.58 8.3 10.5 2.33 4.51 100/200

As shown in Table 1, the self-biased oscillator 100/200 consumes farless power than most of the traditional oscillators. The self-biasedoscillator 100/200 exhibits high power supply rejection ratio, and has ahigher ratio of Kvctrl/Vcc.

FIG. 8 is a system-level diagram of a smart device 1600 comprising aprocessor with the self-biased oscillator 100/200, according to oneembodiment of the disclosure. FIG. 8 also illustrates a block diagram ofan embodiment of a mobile device in which flat surface interfaceconnectors could be used. In one embodiment, the computing device 1600represents a mobile computing device, such as a computing tablet, amobile phone or smart-phone, a wireless-enabled e-reader, or otherwireless mobile device. It will be understood that certain of thecomponents are shown generally, and not all components of such a deviceare shown in device 1600.

In one embodiment, the computing device 1600 includes a first processor1610 with the self-biased oscillator 100 and a second processor 1690with the self-biased oscillator 100, according to the embodimentsdiscussed herein. The self-biased oscillator 100 may be placed in anysuitable area to provide an oscillating signal.

The various embodiments of the present disclosure may also comprise anetwork interface within 1670 such as a wireless interface so that asystem embodiment may be incorporated into a wireless device, forexample, cell phone or personal digital assistant.

In one embodiment, the processor 1610 can include one or more physicaldevices, such as microprocessors, application processors,microcontrollers, programmable logic devices, or other processing means.The processing operations performed by processor 1610 include theexecution of an operating platform or operating system on whichapplications and/or device functions are executed. The processingoperations include operations related to I/O (input/output) with a humanuser or with other devices, operations related to power management,and/or operations related to connecting the computing device 1600 toanother device. The processing operations may also include operationsrelated to audio I/O and/or display I/O.

In one embodiment, the computing device 1600 includes audio subsystem1620, which represents hardware (e.g., audio hardware and audiocircuits) and software (e.g., drivers, codecs) components associatedwith providing audio functions to the computing device. Audio functionscan include speaker and/or headphone output, as well as microphoneinput. Devices for such functions can be integrated into device 1600, orconnected to the computing device 1600. In one embodiment, a userinteracts with the computing device 1600 by providing audio commandsthat are received and processed by processor 1610.

Display subsystem 1630 represents hardware (e.g., display devices) andsoftware (e.g., drivers) components that provide a visual and/or tactiledisplay for a user to interact with the computing device. Displaysubsystem 1630 includes display interface 1632, which includes theparticular screen or hardware device used to provide a display to auser. In one embodiment, display interface 1632 includes logic separatefrom processor 1610 to perform at least some processing related to thedisplay. In one embodiment, display subsystem 1630 includes a touchscreen (or touch pad) device that provides both output and input to auser.

I/O controller 1640 represents hardware devices and software componentsrelated to interaction with a user. I/O controller 1640 is operable tomanage hardware that is part of audio subsystem 1620 and/or displaysubsystem 1630. Additionally, I/O controller 1640 illustrates aconnection point for additional devices that connect to device 1600through which a user might interact with the system. For example,devices that can be attached to the computing device 1600 might includemicrophone devices, speaker or stereo systems, video systems or otherdisplay device, keyboard or keypad devices, or other I/O devices for usewith specific applications such as card readers or other devices.

As mentioned above, I/O controller 1640 can interact with audiosubsystem 1620 and/or display subsystem 1630. For example, input througha microphone or other audio device can provide input or commands for oneor more applications or functions of the computing device 1600.Additionally, audio output can be provided instead of, or in addition todisplay output. In another example, if display subsystem includes atouch screen, the display device also acts as an input device, which canbe at least partially managed by I/O controller 1640. There can also beadditional buttons or switches on the computing device 1600 to provideI/O functions managed by I/O controller 1640.

In one embodiment, the I/O controller 1640 manages devices such asaccelerometers, cameras, light sensors or other environmental sensors,or other hardware that can be included in the computing device 1600. Theinput can be part of direct user interaction, as well as providingenvironmental input to the system to influence its operations (such asfiltering for noise, adjusting displays for brightness detection,applying a flash for a camera, or other features).

In one embodiment, the computing device 1600 includes power management1650 that manages battery power usage, charging of the battery, andfeatures related to power saving operation. Memory subsystem 1660includes memory devices for storing information in device 1600. Memorycan include nonvolatile (state does not change if power to the memorydevice is interrupted) and/or volatile (state is indeterminate if powerto the memory device is interrupted) memory devices. Memory 1660 canstore application data, user data, music, photos, documents, or otherdata, as well as system data (whether long-term or temporary) related tothe execution of the applications and functions of the computing device1600.

Elements of embodiments are also provided as a machine-readable medium(e.g., memory 1660) for storing the computer-executable instructions(e.g., instructions to implement any other processes discussed herein).The machine-readable medium (e.g., memory 1660) may include, but is notlimited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs,EPROMs, EEPROMs, magnetic or optical cards, or other type ofmachine-readable media suitable for storing electronic orcomputer-executable instructions. For example, embodiments of thedisclosure may be downloaded as a computer program (e.g., BIOS) whichmay be transferred from a remote computer (e.g., a server) to arequesting computer (e.g., a client) by way of data signals via acommunication link (e.g., a modem or network connection).

Connectivity 1670 includes hardware devices (e.g., wireless and/or wiredconnectors and communication hardware) and software components (e.g.,drivers, protocol stacks) to enable the computing device 1600 tocommunicate with external devices. The device 1600 could be separatedevices, such as other computing devices, wireless access points or basestations, as well as peripherals such as headsets, printers, or otherdevices.

Connectivity 1670 can include multiple different types of connectivity.To generalize, the computing device 1600 is illustrated with cellularconnectivity 1672 and wireless connectivity 1674. Cellular connectivity1672 refers generally to cellular network connectivity provided bywireless carriers, such as provided via GSM (global system for mobilecommunications) or variations or derivatives, CDMA (code divisionmultiple access) or variations or derivatives, TDM (time divisionmultiplexing) or variations or derivatives, or other cellular servicestandards. Wireless connectivity 1674 refers to wireless connectivitythat is not cellular, and can include personal area networks (such asBluetooth, Near Field, etc), local area networks (such as Wi-Fi), and/orwide area networks (such as WiMax), or other wireless communication.

Peripheral connections 1680 include hardware interfaces and connectors,as well as software components (e.g., drivers, protocol stacks) to makeperipheral connections. It will be understood that the computing device1600 could both be a peripheral device (“to” 1682) to other computingdevices, as well as have peripheral devices (“from” 1684) connected toit. The computing device 1600 commonly has a “docking” connector toconnect to other computing devices for purposes such as managing (e.g.,downloading and/or uploading, changing, synchronizing) content on device1600. Additionally, a docking connector can allow device 1600 to connectto certain peripherals that allow the computing device 1600 to controlcontent output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietaryconnection hardware, the computing device 1600 can make peripheralconnections 1680 via common or standards-based connectors. Common typescan include a Universal Serial Bus (USB) connector (which can includeany of a number of different hardware interfaces), DisplayPort includingMiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI),Firewire, or other type.

The self-biased oscillator 100 discussed herein can be used for wirelesscircuits. In one embodiment, self-biased oscillator 100 is used inblocks 1670, 1680, 1620, 1640, and 1630 to provide oscillating signalswhich have high power supply noise immunity, low power consumption, andsmaller area than traditional oscillators.

Reference in the specification to “an embodiment,” “one embodiment,”“some embodiments,” or “other embodiments” means that a particularfeature, structure, or characteristic described in connection with theembodiments is included in at least some embodiments, but notnecessarily all embodiments. The various appearances of “an embodiment,”“one embodiment,” or “some embodiments” are not necessarily allreferring to the same embodiments. If the specification states acomponent, feature, structure, or characteristic “may,” “might,” or“could” be included, that particular component, feature, structure, orcharacteristic is not required to be included. If the specification orclaim refers to “a” or “an” element, that does not mean there is onlyone of the elements. If the specification or claims refer to “anadditional” element, that does not preclude there being more than one ofthe additional element.

While the disclosure has been described in conjunction with specificembodiments thereof, many alternatives, modifications and variations ofsuch embodiments will be apparent to those of ordinary skill in the artin light of the foregoing description.

For example, the capacitive devices of the first and seconddifferentiators may be controlled independent of one another. In oneembodiment, the capacitive device of the first differentiator is madeadjustable while the capacitive device of the second differentiator isfixed. In another embodiment, capacitive device of the seconddifferentiator is made adjustable while the capacitive device of thefirst differentiator is fixed. In one embodiment, the resistive devicesthe first and second differentiators may be controlled independent ofone another. In one embodiment, the resistive device of the firstdifferentiator is made adjustable while the resistive device of thesecond differentiator is fixed. In another embodiment, resistive deviceof the second differentiator is made adjustable while the resistivedevice of the first differentiator is fixed. In other embodiments,various combinations of fixed and adjustable capacitive and resistivedevices for the first and second differentiators may be used to form anoscillator.

The embodiments of the disclosure are intended to embrace all suchalternatives, modifications, and variations as to fall within the broadscope of the appended claims.

In addition, well known power/ground connections to integrated circuit(IC) chips and other components may or may not be shown within thepresented figures, for simplicity of illustration and discussion, and soas not to obscure the disclosure. Further, arrangements may be shown inblock diagram form in order to avoid obscuring the disclosure, and alsoin view of the fact that specifics with respect to implementation ofsuch block diagram arrangements are highly dependent upon the platformwithin which the present disclosure is to be implemented i.e., suchspecifics should be well within purview of one skilled in the art. Wherespecific details (e.g., circuits) are set forth in order to describeexample embodiments of the disclosure, it should be apparent to oneskilled in the art that the disclosure can be practiced without, or withvariation of, these specific details. The description is thus to beregarded as illustrative instead of limiting.

The following examples pertain to further embodiments. Specifics in theexamples may be used anywhere in one or more embodiments. All optionalfeatures of the apparatus described herein may also be implemented withrespect to a method or process.

For example, in one embodiment the apparatus comprises: a firstdifferentiator with adjustable resistance or capacitance, the firstdifferentiator having an output node and an input node; and a seconddifferentiator with adjustable resistance or capacitance, the seconddifferentiator having an input node coupled to the output node of thefirst differentiator, and having an output node coupled to the inputnode of the first differentiator.

In one embodiment, the first and second differentiators comprise: anamplifier with an input node and an output node; and a resistive devicewith a node coupled to the input node of the amplifier. In oneembodiment, the first and second differentiators comprise: a switchabledevice coupled in series parallel with the resistive device, wherein theswitchable device having a node coupled to the output node of theamplifier. In one embodiment, the switchable device has a resistancecontrollable by a control signal. In one embodiment, the resistivedevice has a resistance controllable by a control signal. In oneembodiment, the amplifier is an inverter or an operational amplifier(OPAMP).

In one embodiment, the first differentiator comprises: a capacitivedevice with a first node coupled to the input node of the firstdifferentiator, and a second node coupled to an input of an amplifier.In one embodiment, the capacitive device is a varactor with acapacitance controllable by a control signal. In one embodiment, thefirst node of the capacitive device is coupled to the output node of thesecond differentiator. In one embodiment, the second differentiatorcomprises: a capacitive device with a first node coupled to the inputnode of the second differentiator, and a second node coupled to an inputof an amplifier. In one embodiment, the capacitive device is a varactorwith a capacitance controllable by a control signal. In one embodiment,the first node of the capacitive device is coupled to the output node ofthe second differentiator.

In one embodiment, the apparatus further comprises a circuit forgenerating a control signal to adjust the resistance or capacitance ofthe first and second differentiators. In one embodiment, the first andsecond differentiators are coupled together for operating as anoscillator. In one embodiment, the output node of the firstdifferentiator has an output signal with an oscillating frequency whichis independent of power supply provided to an amplifier of the firstdifferentiator.

In another example, the apparatus comprises: a first differentiator; anda second differentiator coupled to the first differentiator to form anoscillator having an oscillation frequency independent of the powersupply to the first and second differentiators. In one embodiment, thefirst and second differentiators comprise: an amplifier with an inputnode and an output node; and a resistive device with a node coupled tothe input node of the amplifier. In one embodiment, the first and seconddifferentiators comprise: a switchable device coupled in series orparallel to the resistive device, wherein the switchable device having anode coupled to the output node of the amplifier. In one embodiment, theresistive device has a resistance controllable by a control signal. Inone embodiment, the amplifier is an inverter or an operational amplifier(OPAMP).

In another example, a system comprises: a wireless antenna; and aprocessor operable to communicate with other devices via the wirelessantenna, the processor comprising an oscillator according to theapparatus discussed herein. In one embodiment, the system furthercomprises a display unit.

In another example, a phase or delay locked loop (i.e., circuit)comprises: a phase detector to compare the phases of a reference clocksignal and a feedback signal; and an oscillator to generate the feedbacksignal directly or indirectly, the oscillator according to the apparatusdiscussed herein.

An abstract is provided that will allow the reader to ascertain thenature and gist of the technical disclosure. The abstract is submittedwith the understanding that it will not be used to limit the scope ormeaning of the claims. The following claims are hereby incorporated intothe detailed description, with each claim standing on its own as aseparate embodiment.

What is claimed is:
 1. A phase-locked loop comprising a phase detector,a charge pump, a filter, and a self-biased voltage-controlled oscillatorhaving an oscillating frequency controlled by a control signal, thecontrol signal being coupled to the output of the charge pump, theself-biased voltage-controlled oscillator comprising: a firstdifferentiator having a first output node and a first input node; and asecond differentiator having a second input node coupled to the firstoutput node, and having a second output node coupled to the first inputnode; each of the first and the second differentiators configured withone or both of adjustable resistance and adjustable capacitance, whereinthe oscillating frequency of the voltage-controlled oscillator isindependent of power supply provided to the first and the seconddifferentiators.
 2. The phase-locked loop of claim 1, wherein theoscillating frequency of the voltage-controlled oscillator is a functionof the adjustable resistance and the adjustable capacitance.
 3. Thephase-locked loop of claim 2, wherein the adjustable resistance and theadjustable capacitance of the first and the second differentiators arecontrolled by the control signal.
 4. The phase-locked loop of claim 1,wherein the first and second differentiators each comprises: anamplifier with an input node and an output node; and a resistive devicewith a node coupled to the input node of the amplifier, wherein theoutput node of the amplifier of the first differentiator is coupled tothe first output node, and the output node of the amplifier of thesecond differentiator is coupled to the second output node.
 5. Thephase-locked loop of claim 4, wherein the first and seconddifferentiators comprise: a switchable device coupled in series orparallel to the resistive device, wherein the switchable device having anode coupled to the output node of the amplifier and a resistancecontrollable by the control signal.
 6. The phase-locked loop of claim 4,wherein the resistive device has a resistance controllable by thecontrol signal.
 7. The phase-locked loop of claim 1, wherein the firstdifferentiator comprises: a capacitive device with a first node coupledto the first input node, and a second node coupled to an input of anamplifier.
 8. The phase-locked loop of claim 7, wherein the capacitivedevice is a varactor with a capacitance controllable by the controlsignal.
 9. The phase-locked loop of claim 1, wherein the seconddifferentiator comprises: a capacitive device with a first node coupledto the second input node, and a second node coupled to an input of anamplifier.
 10. The phase-locked loop of claim 9, wherein the capacitivedevice is a varactor with a capacitance controllable by the controlsignal.
 11. A digital phase-locked loop comprising a phase detector, acontroller, a digital filter, and a self-biased digitally-controlledoscillator having an oscillating frequency controlled by a controlsignal filtered by the digital filter and coupled to the controller, theself-biased digitally-controlled oscillator comprising: a firstdifferentiator having a first output node and a first input node; and asecond differentiator having a second input node coupled to the firstoutput node, and having a second output node coupled to the first inputnode; each of the first and the second differentiators configured withone or both of adjustable resistance and adjustable capacitance, whereinthe oscillating frequency of the digitally-controlled oscillator isindependent of power supply provided to the first and the seconddifferentiators.
 12. The phase-locked loop of claim 11, wherein theoscillating frequency of the digitally-controlled oscillator is afunction of the adjustable resistance and the adjustable capacitance.13. The phase-locked loop of claim 12, wherein the adjustable resistanceand the adjustable capacitance of the first and the seconddifferentiators are controlled by the control signal.
 14. Thephase-locked loop of claim 11, wherein the first and seconddifferentiators each comprises: an amplifier with an input node and anoutput node; and a resistive device with a node coupled to the inputnode of the amplifier, wherein the output node of the amplifier of thefirst differentiator is coupled to the first output node, and the outputnode of the amplifier of the second differentiator is coupled to thesecond output node.
 15. The phase-locked loop of claim 14, wherein thefirst and second differentiators comprise: a switchable device coupledin series or parallel to the resistive device, wherein the switchabledevice having a node coupled to the output node of the amplifier and aresistance controllable by the control signal.
 16. The phase-locked loopof claim 11, wherein the first differentiator comprises: a capacitivedevice with a first node coupled to the first input node, and a secondnode coupled to an input of an amplifier.
 17. The phase-locked loop ofclaim 16, wherein the capacitive device is a varactor with a capacitancecontrollable by the control signal.
 18. The phase-locked loop of claim11, wherein the second differentiator comprises: a capacitive devicewith a first node coupled to the second input node, and a second nodecoupled to an input of an amplifier.
 19. The phase-locked loop of claim18, wherein the capacitive device is a varactor with a capacitancecontrollable by the control signal.
 20. A self-biased voltage controlledoscillator, comprising: a first differentiator having a first outputnode and a first input node; and a second differentiator having a secondinput node coupled to the first output node, and having a second outputnode coupled to the first input node; each of the first and the seconddifferentiators configured with one or both of adjustable resistance andadjustable capacitance, wherein the oscillating frequency of thevoltage-controlled oscillator is independent of power supply provided tothe first and the second differentiators, and wherein the oscillatingfrequency of the voltage-controlled oscillator is a function of theadjustable resistance and the adjustable capacitance both controllableby a control signal received by the first and the seconddifferentiators.